product brief may 2001 a[20:0] 21 ce# oe# byte# we# 15 dq[14:0] dq[15]/a[-1] reset# ry/by# wp#/acc logic diagram HY29DS322/hy29ds323 32 megabit (4m x 8/2m x16) super-low voltage, dual bank, simultaneous read/write, flash memory key features single power supply operation ? read, program, and erase operations from 1.8 to 2.2 v (2.0v 10%) ? ideal for battery-powered applications simultaneous read/write operations ? host system can program or erase in one bank while simultaneously reading from any sector in the other bank with zero latency between read and write operations high performance ? 100, 110 and 120 ns access time versions ultra low power consumption (typical values) ? automatic sleep mode current: 5 a ? standby mode current: 5 a ? read current: 5 ma (at 5 mhz) ? program/erase current: 20 ma boot-block sector architecture with 71 sectors in two banks for fast in-system code changes secured sector: an extra 64 kbyte sector that can be: ? factory locked and identifiable: 16 bytes available for a secure, random factory electronic serial number ? customer lockable: can be read, program- med, or erased just like other sectors flexible sector architecture ? sector protection allows locking of a sector or sectors to prevent program or erase operations within that sector ? temporary sector unprotect allows changes in locked sectors (requires high voltage on reset# pin) automatic erase algorithm erases any combination of sectors or the entire chip automatic program algorithm writes and verifies data at specified addresses compliant with common flash memory interface (cfi) specification minimum 100,000 write cycles per byte/ word compatible with jedec standards ? pinout and software compatible with single-power supply flash devices ? superior inadvertent write protection data# polling and toggle bits ? provide software confirmation of completion of program or erase operations ready/busy# pin ? provides hardware confirmation of completion of program or erase operations erase suspend ? suspends an erase operation to allow programming data to or reading data from a sector in the same bank ? erase resume can then be invoked to complete the suspended erasure hardware reset pin (reset#) resets the device to reading array data wp#/acc input pin ? write protect (wp#) function allows hardware protection of two outermost boot sectors, regardless of sector protect status ? acceleration (acc) function provides accelerated program times fast program and erase times ? sector erase time: 2 sec typical ? byte/word program time utilizing acceleration function: 10 s typical space efficient packaging ? 48-pin tsop and 48-ball fbga packages
2 pb may 01 HY29DS322/hy29ds323 general description the HY29DS322/hy29ds323 (hy29ds32x) is a 32 mbit, 2.0 volt-only cmos flash memory orga- nized as 4,194,304 (4m) bytes or 2,097,152 (2m) words. the device is available in 48-pin tsop and 48-ball fbga packages. word-wide data (x16) appears on dq[15:0] and byte-wide (x8) data appears on dq[7:0]. the hy29ds32x flash memory array is organized into 71 sectors in two banks. bank 1 contains eight 8 kbyte boot/parameter sectors and 7 or 15 larger sectors of 64 kbytes each, depending on the version of the device. bank 2 contains the rest of the memory array, organized as 56 or 48 sectors of 64 kbytes: the device features simultaneous read/write op- eration, which allows the host system to invoke a program or erase operation in one bank and im- mediately and simultaneously read data from the other bank, except if that bank has any sectors marked for erasure, with zero latency. this re- leases the system from waiting for the completion of program or erase operations, thus improving overall system performance. the hy29ds32x can be programmed and erased in-system with a single 2.0 volt 10% v cc supply. internally generated and regulated voltages are provided for program and erase operations, so that the device does not require a higher voltage v pp power supply to perform those functions. the de- vice can also be programmed in standard eprom programmers. access times as low as 100ns are offered for timing compatibility with the zero wait state requirements of high speed microproces- sors. to eliminate bus contention, the hy29ds32x has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. the device is compatible with the jedec single- power-supply flash command set standard. com- mands are written to the command register using standard microprocessor write timings, from where they are routed to an internal state-machine that controls the erase and programming circuits. device programming is performed a byte/word at a time by executing the four-cycle program com- mand write sequence. this initiates an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. faster programming times can be achieved by placing the hy29ds32x in the unlock bypass mode, which requires only two write cycles to program data in- stead of four. the hy29ds32x?s sector erase architecture al- lows any number of array sectors, in one or both banks, to be erased and reprogrammed without affecting the data contents of other sectors. de- vice erasure is initiated by executing the erase command sequence. this initiates an internal al- gorithm that automatically preprograms the sec- tor before executing the erase operation. as dur- ing programming cycles, the device automatically times the erase pulse widths and verifies proper cell margin. hardware sector group protection optionally disables both program and erase op- erations in any combination of the sector groups, while temporary sector group unprotect, which requires a high voltage on one pin, allows in-sys- tem erasure and code changes in previously pro- tected sector groups. erase suspend enables the user to put erase on hold in a bank for any period of time to read data from or program data to any sector in that bank that is not selected for era- sure. true background erase can thus be achieved. because the hy29ds32x features si- multaneous read/write capability, there is no need to suspend to read from a sector located within a bank that does not contain sectors marked for era- sure. the device is fully erased when shipped from the factory. addresses and data needed for the programming and erase operations are internally latched during write cycles. the host system can detect comple- tion of a program or erase operation by observing the ry/by# pin or by reading the dq[7] (data# polling) and dq[6] (toggle) status bits. hardware data protection measures include a low v cc de- tector that automatically inhibits write operations during power transitions. after a program or erase cycle has been com- pleted, or after assertion of the reset# pin (which terminates any operation in progress), the device is ready to read data or to accept another com 1 k n a b 2 k n a b 2 2 3 s d 9 2 y h w k 4 / b k 8 x 8 w k 2 3 / b k 4 6 x 6 5 w k 2 3 / b k 4 6 x 7 3 2 3 s d 9 2 y h w k 4 / b k 8 x 8 w k 2 3 / b k 4 6 x 8 4 w k 2 3 / b k 4 6 x 5 1
3 pb may 01 HY29DS322/hy29ds323 state control we# ce# reset# byte# command register a[20:0], a-1 v cc detector timer erase voltage generator and sector switches program voltage generator address latch x-decoder y-decoder 32 mb flash memory array (2 banks, 71 sectors) 0.5 mb flash security sector y-gating data latch i/o buffers i/o control ry/by# dq[15:0] cfi control cfi data memory a[20:0], a-1 wp#/acc oe# block diagram mand. reading data out of the device is similar to reading from other flash or eprom devices. the secured sector is an extra 64 kbyte sector capable of being permanently locked at the fac- tory or by customers. the secured indicator bit (accessed via the electronic id mode) is perma- nently set to a 1 if the part is factory locked, and permanently set to a 0 if customer lockable. this way, customer lockable parts can never be used to replace a factory locked part. factory locked parts provide several options. the secured sec- tor may store a secure, random 16-byte esn (elec- tronic serial number), customer code programmed at the factory, or both. customer lockable parts may utilize the secured sector as bonus space, reading and writing like any other flash sector, or may permanently lock their own code there. the wp#/acc pin provides access to two func- tions. the write protect function provides a hard- ware method of protecting certain boot sectors without using a high voltage. the accelerate func- tion speeds up programming operations, and is intended primarily to allow faster manufacturing throughput. two power-saving features are embodied in the hy29ds32x. when addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. the host can also place the device into the standby mode. power consump- tion is greatly reduced in both these modes. common flash memory interface (cfi) to make flash memories interchangeable and to encourage adoption of new flash technologies, major flash memory suppliers developed a flex- ible method of identifying flash memory sizes and configurations in which all necessary flash device parameters are stored directly on the device. parameters stored include memory size, byte/word configuration, sector configuration, necessary volt- ages and timing information. this allows one set of software drivers to identify and use a variety of different, current and future flash products. the standard which details the software interface nec- essary to access the device to identify it and to determine its characteristics is the common flash memory interface (cfi) specification. the hy29ds32x is fully compliant with this specification.
4 pb may 01 HY29DS322/hy29ds323 signal descriptions e m a n e p y t n o i t p i r c s e d ] 0 : 0 2 [ as t u p n i . h g i h e v i t c a , s s e r d d a 2 5 1 , 7 9 0 , 2 f o e n o t c e l e s s t u p n i 1 2 e s e h t , e d o m d r o w n i e s e h t , e d o m e t y b n i . s n o i t a r e p o e t i r w r o d a e r r o f y a r r a e h t n i h t i w s d r o w ) m 2 ( 4 0 3 , 4 9 1 , 4 f o e n o t c e l e s o t ) b s l ( t u p n i ] 1 - [ a / ] 5 1 [ q d e h t h t i w d e n i b m o c e r a s t u p n i . s n o i t a r e p o e t i r w r o d a e r r o f y a r r a e h t n i h t i w s e t y b ) m 4 ( , ] 1 - [ a / ] 5 1 [ q d ] 0 : 4 1 [ q d s t u p t u o / s t u p n i e t a t s - i r t h g i h e v i t c a , s u b a t a d h t a p a t a d t i b - 6 1 a e d i v o r p s n i p e s e h t , e d o m d r o w n i . h t a p a t a d t i b - 8 n a e d i v o r p ] 0 : 7 [ q d , e d o m e t y b n i . s n o i t a r e p o e t i r w d n a d a e r r o f ] 8 : 4 1 [ q d . t u p n i s s e r d d a e t y b t i b - 2 2 e h t f o b s l e h t s a d e s u s i ] 1 - [ a / ] 5 1 [ q d d n a . . e d o m e t y b n i d e t a t s - i r t n i a m e r d n a d e s u n u e r a # e t y bt u p n i w o l e v i t c a , e d o m e t y b . e d o m d r o w s t c e l e s h g i h , e d o m e t y b s t c e l e s w o l . # e ct u p n i . w o l e v i t c a , e l b a n e p i h c r o m o r f a t a d d a e r o t d e t r e s s a e b t s u m t u p n i s i h t e h t d n a d e t a t s - i r t s i s u b a t a d e h t , h g i h n e h w . x 2 3 s d 9 2 y h e h t o t a t a d e t i r w . e d o m y b d n a t s e h t n i d e c a l p s i e c i v e d # e ot u p n i w o l e v i t c a , e l b a n e t u p t u o s n o i t a r e p o d a e r r o f d e t r e s s a e b t s u m t u p n i s i h t . e r a e c i v e d e h t m o r f s t u p t u o a t a d , h g i h n e h w . s n o i t a r e p o e t i r w r o f d e t a g e n d n a . e t a t s e c n a d e p m i h g i h e h t n i d e c a l p e r a s n i p s u b a t a d e h t d n a d e l b a s i d # e wt u p n i . w o l e v i t c a , e l b a n e e t i r w s e c n e u q e s d n a m m o c r o s d n a m m o c f o g n i t i r w s l o r t n o c s i # e w n e h w e c a l p s e k a t n o i t a r e p o e t i r w a . s n o i t a r e p o e c i v e d s u o i r a v r o f . h g i h s i # e o d n a w o l o s l a s i # e c e l i h w d e t r e s s a # t e s e rt u p n i . w o l e v i t c a , t e s e r e r a w d r a h e h t g n i t t e s e r f o d o h t e m e r a w d r a h a s e d i v o r p y l e t a i d e m m i t i , t e s e r s i e c i v e d e h t n e h w . e t a t s y a r r a d a e r e h t o t x 2 3 s d 9 2 y h e t i r w / d a e r l l a d n a d e t a t s - i r t s i s u b a t a d e h t . s s e r g o r p n i n o i t a r e p o y n a s e t a n i m r e t d e t r e s s a s i # t e s e r e l i h w . d e t r e s s a s i t u p n i e h t e l i h w d e r o n g i e r a s d n a m m o c . e d o m y b d n a t s e h t n i e b l l i w e c i v e d e h t # y b / y r t u p t u o n i a r d n e p o . s u t a t s y s u b / y d a e r n i s i d n a m m o c e s a r e r o e t i r w a r e h t e h w s e t a c i d n i # e w l a n i f e h t f o e g d e g n i s i r e h t r e t f a d i l a v . d e t e l p m o c n e e b s a h r o s s e r g o r p y l e v i t c a s i e c i v e d e h t e l i h w w o l s n i a m e r . e c n e u q e s d n a m m o c a f o e s l u p . a t a d y a r r a d a e r o t y d a e r s i t i n e h w h g i h s e o g d n a , g n i s a r e r o a t a d g n i m m a r g o r p c c a / # p wt u p n i v ( e t a r e l e c c a / w o l e v i t c a , t c e t o r p e t i r w h h . ) n o i t c n u f t c e t o r p e t i r wv t a n i p s i h t g n i c a l p : l i e s a r e d n a m a r g o r p s e l b a s i d e r a s r o t c e s d e t c e f f a e h t . s r o t c e s t o o b e t y b k 8 t h g i e e h t f o o w t n i s n o i t a r e p o . e c i v e d t o o b - p o t a n i 0 7 s d n a 9 6 s r o , e c i v e d t o o b - m o t t o b a n i 1 s d n a 0 s s r o t c e s v t a d e c a l p s i n i p e h t f i h i o t s t r e v e r s r o t c e s o w t e s o h t f o e t a t s n o i t c e t o r p e h t , r o t c e s e h t g n i s u d e t c e t o r p n u r o d e t c e t o r p e b o t t e s t s a l e r e w y e h t r e h t e h w . x 2 3 s d 9 2 y h e h t f o y t i l i b a p a c n o i t c e t o r p n u d n a n o i t c e t o r p p u o r g : n o i t c n u f e t a r e l e c c av f i h h k c o l n u e h t s r e t n e e c i v e d e h t , t u p n i s i h t o t d e i l p p a s i e h t s e s u d n a , s r o t c e s d e t c e t o r p y n a s t c e t o r p n u y l i r a r o p m e t , e d o m s s a p y b . s n o i t a r e p o m a r g o r p r o f d e r i u q e r e m i t e h t e c u d e r o t n i p e h t n o e g a t l o v r e h g i h s a e c n e u q e s d n a m m o c m a r g o r p e l c y c - o w t e h t e s u n e h t d l u o w m e t s y s e h t ( v g n i v o m e r ) . e d o m s s a p y b k c o l n u e h t y b d e r i u q e r h h e h t s n r u t e r n i p e h t m o r f . n o i t a r e p o l a m r o n o t e c i v e d v t a e b t o n t s u m n i p s i h t h h , g n i m m a r g o r p d e t a r e l e c c a n a h t r e h t o s n o i t a r e p o r o f t l u s e r y a m d e t c e n n o c n u r o g n i t a o l f n i p e h t g n i v a e l . t l u s e r y a m e g a m a d e c i v e d r o . n o i t a r e p o e c i v e d t n e t s i s n o c n i n i v c c - - . y l p p u s r e w o p t l o v - 2 v s s - - . d n u o r g l a n g i s d n a r e w o p
5 pb may 01 HY29DS322/hy29ds323 tsop48 a[11] a[10] 5 6 a[9] a[8] 7 8 a[19] a[20] 9 10 we# reset# 11 12 nc wp#/acc 13 14 ry/by# a[18] 15 16 a[17] a[7] 17 18 a[6] a[5] 19 20 a[15] a[14] 1 2 a[13] a[12] 3 4 a[4] a[3] 21 22 a[2] a[1] 23 24 dq[7] dq[14] 44 43 dq[6] dq[13] 42 41 dq[5] dq[12] 40 39 dq[4] v cc 38 37 dq[11] dq[3] 36 35 dq[10] dq[2] 34 33 dq[9] dq[1] 32 31 dq[8] dq[0] 30 29 a[16] byte# 48 47 v ss dq[15]/a[-1] 46 45 oe# v ss 28 27 ce# a[0] 26 25 48-ball fbga - top view, balls facing down c7 a[13] d7 a[12] e7 a[14] f7 a[15] g7 a[16] h7 v ih j7 dq[15] k7 v ss c6 a[9] d6 a[8] e6 a[10] f6 a[11] g6 dq[7] h6 dq[14] j6 dq[13] k6 dq[6] c5 we# d5 reset# e5 nc f5 a[19] g5 dq[5] h5 dq[12] j5 v cc k5 dq[4] c4 ry/by# d4 wp#/acc e4 a[18] f4 a[20] g4 dq[2] h4 dq[10] j4 dq[11] k4 dq[3] c3 a[7] d3 a[17] e3 a[6] f3 a[5] g3 dq[0] h3 dq[8] j3 dq[9] k3 dq[1] c2 a[3] d2 a[4] e2 a[2] f2 a[1] g2 a[0] h2 ce# j2 oe# k2 v ss pin configurations
6 pb may 01 HY29DS322/hy29ds323 ? 2001 by hynix semiconductor america inc. all rights re- served. no part of this document may be copied or repro- duced in any form or by any means without the prior written consent of hynix semiconductor inc. or hynix semiconductor america inc. (collectively ? hynix ? ). this document describes a product currently under design by hynix. the information in this document is subject to change without notice. hynix shall not be responsible for any errors that may appear in this document and makes no commitment to update or keep current the information contained in this docu- ment. hynix advises its customers to obtain the latest version of the device specification to verify, before placing orders, that the information being relied upon by the customer is current. memory sales and marketing division flash memory business unit hynix semiconductor inc. hynix semiconductor america inc. 10 fl., hynix youngdong building 3101 north first street 89, daechi-dong san jose, ca 95134 kangnam-gu usa seoul, korea telephone: (408) 232-8800 telephone: +82-2-580-5000 fax: (408) 232-8805 fax: +82-2-3459-3990 http://www.us.hynix.com http://www.hynix.com important notice
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